The memory (RAM) is powered on, and the power management circuitry ensures that the memory voltage and timing are adjusted according to the system's requirements.
The PSU sends a "Power OK" (gray wire) signal to the SIO. The motherboard logic then generates a System Power Good signal for the PCH and CPU.
Before the power button is pressed (when the PC is plugged in but "off"):
The PCH asserts (Status Sleep 5) and SLP_S4# (Status Sleep 4) high (typically 3.3V).
[Secondary Rails Stable] ➔ [VCCIN / VCORE VRM Enabled] ➔ [PSU sends PWR_OK] ➔ [SIO sends SYS_PWROK] ➔ [PLTRST# / CPURST# Released] Step 10: VRM Activation (VCORE) desktop motherboard power sequence pdf
These resources can be found in various places. Official design guides are often available from chipset manufacturers like Intel, which release extensive documentation on their platforms, including detailed timing and housekeeping specifications. Resources like the "Motherboard Power On Sequence" PDF offer a technical overview of key pins and signals. Additionally, community-driven repair sites frequently share valuable schematics and power sequence guides for specific motherboard models, such as those for Gigabyte and ASUS motherboards.
The PSU immediately sends to the motherboard via Pin 9 of the 24-pin ATX connector.
When a motherboard fails to start, technicians use this sequence to find the breakdown point. A chart typically shows: Signal Names: Expected Voltage: 3.3V3.3 cap V Component Locations: Where to measure on the motherboard. Key Troubleshooting Signals No 5VSB5 cap V cap S cap B : Likely a bad PSU. No : Likely a bad Super I/O or PCH.
The internal circuitry of the ATX power supply detects the grounded PS_ON# and activates its main switching transformers. Step 8: Main Rail Delivery The memory (RAM) is powered on, and the
The Southbridge responds by releasing "Sleep" signals— SLP_S4 and SLP_S3 —which travel back to the SIO, signaling it to fully power on the system. 3. Full Power-On (S0 State)
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is not received, the motherboard will not proceed to turn on the CPU, as it assumes the power is unstable. 6. VRM Activation ( Vcorecap V sub c o r e end-sub
Once the PCH is active and ready, it tells the SIO (or directly, the SMPS) to activate the main power rails by pulling the PSON# signal low (0V). Before the power button is pressed (when the
Power-down / sleep reverse: SLP signals, OS request, EC deasserts PS_ON#, VRMs ramp down in safe order, clocks stop, PWR_OK deasserts, PSU turns off main rails; +5VSB remains.
The CMOS battery powers the Real-Time Clock (RTC), and the crystal oscillator starts vibrating at a specific frequency (usually 32.768 KHz) to keep the system's heartbeat steady.
: Covers new generation signal names like DPWROK and H/W Monitor. VRM circuit or a specific troubleshooting guide for a motherboard that won't turn on Motherboard Power Sequence Overview | PDF - Scribd
The moment the power button is pressed:
Once standby voltages and clocks are stable, the motherboard waits for user input. This phase involves a rigorous digital handshake between the SIO and the PCH.
